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Specifications
Length:
2.67mm
Width:
2.45mm
Operating Temperature:
-40℃~+110℃
Interface:
I2C
Measurement Type:
Color Recognition
Voltage - Supply:
2.5V~3.6V
Photoperceptivity:
176klx
Mfr. Part #:
VEML6046X00
Package:
SMD,2.7x2.5mm
Key Attributes
Model Number:
VEML6046X00
Product Description
Product Overview
The VEML6046X00 is a high-accuracy, 16-bit resolution RGBIR sensor in a miniature 2.67 mm x 2.45 mm package. It features sensitive photodiodes, a low-noise amplifier, a 16-bit A/D converter, and supports I2C bus communication with an additional interrupt feature. This AEC-Q100 qualified sensor is designed for automotive applications, including display backlight controls, infotainment systems, rear-view mirror dimming, interior lighting, head-up displays, color recognition, CCT measurement, and mood lighting.
Product Attributes
- Brand: Vishay Semiconductors
- Certifications: AEC-Q100 qualified
- Material categorization: For definitions of compliance see www.vishay.com/doc?99912
Technical Specifications
| Part Number | Operating Voltage Range (V) | I2C Bus Voltage Range (V) | Peak Sensitivity (nm) | Ambient Light Range (lx) | Ambient Light Resolution (lx) | ADC Resolution | Output Code |
| VEML6046X00 | 2.5 to 3.6 | 1.7 to 3.6 | 600 (R), 550 (G), 470 (B), 820 (IR) | 0 to 176,000 | 0.0053 | 16 bit | I2C |
| Parameter | Symbol | Min. | Typ. | Max. | Unit | Notes |
| ASIC Supply voltage | VDD | 2.5 | 3.3 | 3.6 | V | |
| Supply current, Shutdown state | IDD | 0.5 | A | (1) VDD = VBUS | ||
| Supply current, Shutdown state | IDD | 1.2 | A | (1) VDD = VBUS = 3.0 V | ||
| Supply current, Shutdown state | IDD | 3.1 | A | (1) VDD = 3.6 V, VBUS = 1.7 V | ||
| Supply current, Active state | IDD | 370 | A | VDD = 3.3 V | ||
| I2C clock rate range | fSCL | 10 | 400 | kHz | ||
| I2C signal input, logic high | VIH | 0.7 x VBUS | 3.6 | V | VBUS = VDD | |
| I2C signal input, logic high | VIH | 0.85 x VBUS | V | VBUS VDD | ||
| I2C signal input, logic low | VIL | -0.3 | 0.3 x VBUS | V | VBUS = VDD | |
| I2C signal input, logic low | VIL | -0.3 | 0.2 x VBUS | V | VBUS VDD | |
| Digital current out (low, current sink) | Iol | 3 | mA | |||
| Digital resolution (LSB count) | 0.0053 | lx/count | With RGB_GAIN = x 2, RGB_IT = 400 ms, RGB_PDDIV = 2/2 PD | |||
| Detectable maximum illuminance | EV max. | 176,000 | lx | With RGB_GAIN = x 0.5, RGB_IT = 6.25 ms, RGB_PDDIV = 1/2 PD | ||
| Dark offset | R, G, B, IR | -2 | step | With RGB_GAIN = x 1, RGB_IT = 400 ms, RGB_PDDIV = 2/2 PD |
| Parameter | Symbol | Standard Mode (1) Min. | Standard Mode (1) Max. | Fast Mode (1) Min. | Fast Mode (1) Max. | Unit |
| Clock frequency | f(SMBCLK) | 10 | 100 | 10 | 400 | kHz |
| Bus free time between start and stop condition | t(BUF) | 4.7 | 1.3 | s | ||
| Hold time after (repeated) start condition; after this period, the first clock is generated | t(HDSTA) | 4.0 | 0.6 | s | ||
| Repeated start condition setup time | t(SUSTA) | 4.7 | 0.6 | s | ||
| Stop condition setup time | t(SUSTO) | 4.0 | 0.6 | s | ||
| Data hold time | t(HDDAT) | 0 | 3450 | 0 | 900 | ns |
| Data setup time | t(SUDAT) | 250 | 100 | ns | ||
| I2C clock (SCK) low period | t(LOW) | 4.7 | 1.3 | s | ||
| I2C clock (SCK) high period | t(HIGH) | 4.0 | 0.6 | s | ||
| Detect clock / data low timeout | t(TIMEOUT) | 25 | 35 | ms | ||
| Clock / data fall time | t(F) | 300 | 300 | ns | ||
| Clock / data rise time | t(R) | 1000 | 300 | ns |
2410301847_VISHAY-VEML6046X00_C20346082.pdf
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