Product Description
The MS91051 is a configurable analog front-end for Non-Dispersive Infrared (NDIR) sensors. It features a dual-channel design with a programmable gain amplifier (PGA) and offset cancellation for the "dark phase." The device supports multiple thermopile sensors due to its programmability, outputting a voltage proportional to the thermopile voltage. It includes an adjustable common-mode generator (1.15V or 2.59V) to enhance output dynamic range and dedicated pins (A0, A1) for external signal filtering (high-pass, low-pass, or band-pass) to remove out-of-band noise. Programming is done via an SPI interface. The MS91051 is suitable for applications requiring precise gas sensing, including NDIR sensors, demand-controlled ventilation, building monitoring, automotive CO2 and alcohol detection, industrial safety, and greenhouse gas/freon detection.
Product Attributes
- Brand: Relmon
- Origin: China
- Part Number: MS91051
- Package: TSSOP14
Technical Specifications
| Parameter | Symbol | Test Conditions | Min | Typical | Max | Unit |
| Power Supply | ||||||
| Supply Voltage | VDD | 2.7 | 3.3 | 5.5 | V | |
| Digital I/O Voltage | VIO | 2.7 | 3.3 | 5.5 | V | |
| Supply Current (All analog modules ON) | IDD | 3.1 | 3.9 | 4.2 | mA | |
| Shutdown Supply Current (All analog modules OFF) | 45 | 75 | 121 | A | ||
| Digital Supply Current | 8 | A | ||||
| Programmable Gain Amplifier (PGA1) | ||||||
| Bias Current | IBIAS | RL=10k, CL =15pF | 5 | 200 | pA | |
| Max Input Signal (High Gain Mode) | VINMAX_HGM | Before limiting, including dark voltage and signal | 2 | mV | ||
| Max Input Signal (Low Gain Mode) | VINMAX_LGM | 12 | mV | |||
| Input Offset Voltage | VOS | -165 | V | |||
| Gain (High Gain Mode) | G_HGM | 246 | V/V | |||
| Gain (Low Gain Mode) | G_LGM | 41 | V/V | |||
| Gain Error | GE | All gains | 2.5 | % | ||
| Output Voltage Range | VOUT | 0.5 | 0.5*VDD | V | ||
| Phase Delay | PhDly | 1mV input, HGM, measured at Vdd/2 | 6 | s | ||
| Phase Delay vs. Temperature | TcPhDly | 1mV input, HGM, measured at Vdd/2 | 416 | ns | ||
| Small Signal Bandwidth | SSBW | Vin = 1mVpp, Gain = 250 V/V | 18 | kHz | ||
| Input Capacitance | Cin | 100 | pF | |||
| Programmable Gain Amplifier (PGA2) | ||||||
| Max Input Signal | VINMAX | GAIN=4V/V | 1.65 | V | ||
| Min Input Signal | VINMAN | 0.82 | V | |||
| Gain | G | 4 programmable gains | 4 to 32 | dB | ||
| Gain Error | GE | All gains | 2.5 | % | ||
| Output Voltage Range | VOUT | 0.2*VDD | 0.2*VDD | V | ||
| Phase Delay | PhDly | 100mV input, 35kHz sine, Gain=8, measured at 1.65V, RL=10k | 1 | s | ||
| Phase Delay vs. Temperature | TcPhDly | 250mV input, 35kHz sine, Gain=8, measured at VDD/2 | 84 | ns | ||
| Small Signal Bandwidth | SSBW | Gain = 32 V/V | 360 | kHz | ||
| Input Capacitance | Cin | 5 | pF | |||
| Combined PGA1 & PGA2 | ||||||
| Input Noise Density | en | 86K resistor, 5Hz, Gain=7986 | 30 | nVHz | ||
| Input Referred Integrated Noise | Includes current and voltage noise, 86K resistor, 0.1-10Hz, Gain=7986 | 0.1 to 0.12*4 | Vrms | |||
| Gain | GAIN | PGA1 GAIN=42, PGA2 GAIN=4 | 167 | V/V | ||
| Gain | GAIN | PGA1 GAIN=42, PGA2 GAIN=8 | 335 | V/V | ||
| Gain | GAIN | PGA1 GAIN=42, PGA2 GAIN=16 | 669 | V/V | ||
| Gain | GAIN | PGA1 GAIN=42, PGA2 GAIN=32 | 1335 | V/V | ||
| Gain | GAIN | PGA1 GAIN=250, PGA2 GAIN=4 | 1002 | V/V | ||
| Gain | GAIN | PGA1 GAIN=250, PGA2 GAIN=8 | 2004 | V/V | ||
| Gain | GAIN | PGA1 GAIN=250, PGA2 GAIN=16 | 4003 | V/V | ||
| Gain | GAIN | PGA1 GAIN=250, PGA2 GAIN=32 | 7986 | V/V | ||
| Gain Error | GE | All gains | 5 | % | ||
| Gain Temperature Coefficient | TCCGE | Gain = 167 to 1335 V/V | 6 | ppm/C | ||
| Gain Temperature Coefficient | TCCGE | Gain = 1002 to 7986 V/V | 20 | ppm/C | ||
| Power Supply Rejection Ratio | PSRR | DC, 3.0V to 3.6V supply, gain = 1002V/V | 90 | 110 | dB | |
| Phase Delay | PhDly | 1mV input, gain=1002 V/V, measured at midpoint | 9 | s | ||
| Phase Delay vs. Temperature | TCPhDly | 1mV input, gain=1002 V/V, measured at midpoint | 300 | ns | ||
| Output Offset Voltage Temp Drift | TCVOS | GAIN=167V/V | 70 | V/C | ||
| Output Offset Voltage Temp Drift | TCVOS | GAIN=335V/V | 100 | V/C | ||
| Output Offset Voltage Temp Drift | TCVOS | GAIN=669V/V | 160 | V/C | ||
| Output Offset Voltage Temp Drift | TCVOS | GAIN=1335V/V | 290 | V/C | ||
| Output Offset Voltage Temp Drift | TCVOS | GAIN=1002V/V | 230 | V/C | ||
| Output Offset Voltage Temp Drift | TCVOS | GAIN=2004V/V | 420 | V/C | ||
| Output Offset Voltage Temp Drift | TCVOS | GAIN=4003V/V | 800 | V/C | ||
| Output Offset Voltage Temp Drift | TCVOS | GAIN=7986V/V | 1550 | V/C | ||
| Common-Mode Generator | ||||||
| Common-Mode Voltage | VCM | VDD=3.3V | 1.15 | V | ||
| Common-Mode Voltage | VCM | VDD=5V | 2.59 | V | ||
| Common-Mode Voltage Accuracy | 2 | % | ||||
| Common-Mode Output Load Capacitance | CLOAD | 10 | nF | |||
| SPI Interface | ||||||
| Logic High Input Voltage | VIH | 0.7VDD | V | |||
| Logic Low Input Voltage | VIL | 0.8 | V | |||
| Logic High Output Voltage | VOH | 2.6 | V | |||
| Logic Low Output Voltage | VOL | 0.4 | V | |||
| Digital Input Leakage Current | IIH/IIL | -100 | 200 | nA | ||
| SPI Timing Parameters | ||||||
| Wake-up Time | tWU | 1 | ms | |||
| Continuous Clock Frequency | fSCLK | 10 | MHz | |||
| SCLK High Pulse Width | tPH | 0.4/fSCLK | ns | |||
| SCLK Low Pulse Width | tPL | 0.4/fSCLK | ns | |||
| CSB Setup Time | tCSS | 10 | ns | |||
| CSB Hold Time | tCSH | 10 | ns | |||
| SDI Setup Time before SCLK rising edge | tSU | 10 | ns | |||
| SDI Hold Time before SCLK rising edge | tSH | 10 | ns | |||
| SDO Disable Time after CSB rising edge | tDOD1 | 45 | ns | |||
| SDO Disable Time after 16th SCLK rising edge | tDOD2 | 45 | ns | |||
| SDO Enable Time at 8th SCLK falling edge | tDOE | 35 | ns | |||
| SDO Access Time after SCLK falling edge | tDOA | 35 | ns | |||
| SDO Hold Time after SCLK falling edge | tDOH | 5 | ns | |||
| SDO Rise Time | tDOR | 5 | ns | |||
| SDO Fall Time | tDOF | 5 | ns | |||
1912261709_Hangzhou-Ruimeng-Tech-MS91051_C475020.pdf
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