Product Overview
The AS5132 is a high-speed, 360-degree programmable magnetic position sensor designed for accurate angular measurement. This system-on-chip integrates Hall elements, analog front-end, and digital signal processing, requiring only a simple two-pole magnet for operation. It provides absolute angle measurement with 8.5-bit resolution, outputting digital data via a serial interface and a PWM signal. Additional U,V,W outputs are available for brushless DC motor commutation, with an optional incremental signal. The device also outputs magnetic field strength and features one-time programmable memory for zero angle position. Its contactless sensing principle makes it ideal for harsh environments, offering robustness against misalignment, airgap variations, temperature fluctuations, and stray magnetic fields.
Product Attributes
- Brand: ams OSRAM Group
- Certifications: Fully automotive qualified to AEC-Q100, grade 0
Technical Specifications
| Parameter | Conditions | Min | Typ | Max | Units | Notes |
| System Parameters | ||||||
| VDD Positive supply voltage | 4.4 | 5.5 | V | |||
| VDDP Positive supply voltage periphery | 3.0 | 5.5 | V | |||
| IDD Operating current | No load on outputs. Supply current can be reduced by using stronger magnets. | 15 | 22 | mA | ||
| N Resolution | 8.5 | Bit | ||||
| TPwrUp Power up time | 4100 | s | ||||
| ts Tracking rate | Step rate of tracking ADC; 1 step = 1 | 5.2 | s/step | |||
| INLcm Accuracy | Centered magnet | -2 | 2 | Deg | ||
| INLcm Accuracy | Within horizontal displacement radius | -3 | 3 | Deg | ||
| tdelay Propagation delay | Internal signal processing time | 22 | s | |||
| TN Transition noise peak-peak | 1.41 | Deg | ||||
| Magnet Specifications | ||||||
| BZ Magnetic input range | At die surface | 20 | 80 | mT | ||
| Vi Magnet rotation speed | To maintain locked state (1) | 72,900 | rpm | Maximum rotation speed is dependent on the internal time reference. Maximum value is calculated with lowest sequence over all operating conditions. | ||
| Programming Parameters | ||||||
| VPROG Programming voltage | Static voltage at pin PROG | 8 | 8.5 | V | ||
| IPROG Programming current | During programming | 100 | mA | |||
| TambPROG Programming ambient temperature | 0 | 85 | C | |||
| tPROG Programming time | 2 | 4 | s | |||
| VR,prog Analog readback voltage | During analog readback mode at pin PROG | 0.5 | V | |||
| VR,unprog | 2 | 3.5 | ||||
| DC Characteristics of Digital Inputs | ||||||
| VIH High level input voltage | COM/INC refer to VDD | 0.7*VDDP | VDDP | V | ||
| VIL Low level input voltage | 0 | 0.3*VDDP | V | |||
| ILEAK Input leakage current | 1 | A | ||||
| DC Characteristics of Digital Outputs | ||||||
| VOH High level output voltage | PWM and S have 8mA output load, DIO has 4mA output load. | VDDP-0.5 | VDDP | V | ||
| VOH High level output voltage | VDD-0.5 | VDD | V | U_A, V_B, W_I have 4mA output load. | ||
| VOL Low level output voltage | PWM and S have 8mA output load, DIO, U_A, V_ B, W_I has 4mA output load. | 0 | VSS+0.4 | V | ||
| CL Capacitive load | 35 | pF | ||||
| Timing Characteristics | ||||||
| fCLK Clock frequency normal operation | 5 | 6 | MHz | |||
| fCLKP Clock frequency during OTP programming | 200 | 650 | kHz | |||
| t1 CSn to positive edge of CLK | 150 | ns | ||||
| t2 CSn to drive bus externally | 0 | ns | ||||
| t3 Setup time command bit (data valid to positive edge of CLK) | 50 | ns | ||||
| t4 Hold time command bit (data valid after positive edge of CLK) | 15 | ns | ||||
| t5 Float time (positive edge of CLK for last command bit to bus float) | 0.5 *1/fCLK | ns | ||||
| t6 Bus driving time (positive edge of CLK for last command bit to bus drive) | 0.5 *1/fCLK | ns | ||||
| t7 Data valid time (positive edge of CLK to bus valid) | 0.5 *1/fCLK | 0.5 *1/fCLK + 50 | ns | |||
| t8 Hold time data bit (data valid after positive edge of CLK) | 0.5 *1/fCLK | ns | ||||
| t9 Hold time CSn (positive edge of last CLK to negative edge of CSn) | 0.5 *1/fCLK | ns | ||||
| t10 Bus floating time (positive edge of CSn to float bus) | 50 | ns | ||||
| t11 Setup time data bit @ write access (data valid to positive edge of CLK) | 50 | ns | ||||
| t12 Hold time data bit @ write access (data valid after | ||||||
2504101957_AMS-AS5132-HSST_C28748206.pdf
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