Dual Output Differential Speed and Direction Sensor IC ATS17501
The ATS17501 is a single IC solution designed for rotational position sensing of ferrous gear targets in automotive and industrial electric motor applications. It offers high accuracy speed and direction information, with options for dual-phase gear speed and position signal or simultaneous high-resolution gear speed and direction. The IC is housed in an SG package with an integrated magnetic pellet for enhanced reliability and consistent performance. It features digital circuits and algorithms to eliminate offsets and false transitions, and can be programmed for various applications, including ASIL B(D) utilization with Fault Detection mode.
Product Attributes
- Brand: Allegro MicroSystems
- Package: 4-Pin SIP (suffix SG)
- Material: Lead (Pb) free with 100% matte-tin-plated lead frame
- Certifications: ASIL B(D) compliant (ISO 26262)
Technical Specifications
| Characteristic | Symbol | Notes | Min. | Typ. | Max. | Unit |
| ELECTRICAL SUPPLY CHARACTERISTICS | ||||||
| Supply Voltage | VCC | Voltage across VCC and GND | 4 | 24 | V | |
| Undervoltage Lockout | VCC(UV) | 3.99 | V | |||
| Supply Current | ICC | 10 | 15 | mA | ||
| Reverse Supply Current | IRCC | VCC = 18 V | 10 | mA | ||
| ELECTRICAL PROTECTION CHARACTERISTICS | ||||||
| Supply Clamp Voltage | VCSUPPLY | TA = 25C; ICC = 18 mA | 28 | V | ||
| Reverse Supply Clamp Voltage | VRCSUPPLY | TA = 25C; ICC = 3 mA | 18 | V | ||
| Output Clamp Voltage | VOUT | TA = 25C; IOUT = 3 mA | 28 | V | ||
| Output Current Internal Limiter | IOUT(LIM) | Current limited by design for short circuit event on OUTA and OUTB independently; low impedance output state | 30 | 55 | 85 | mA |
| POWER-ON CHARACTERISTICS | ||||||
| Power-On State | POS | For OUTA and OUTB VOUT(HIGH) | V | |||
| Power-On Time | tPO | Time from VCC > VCC(min) to when sensor IC output is valid | 1 | ms | ||
| CALIBRATION CHARACTERISTICS | ||||||
| First Output Edge | Amount of target rotation with constant direction following power-on until first electrical output transition; Dynamic Threshold option; see Figure 1 | 1 | TCYLE | |||
| Initial Calibration | Amount of target rotation with constant direction following power-on until calibration is complete; Dynamic Threshold option; see Figure 1 | 2 | TCYLE | |||
| OUTPUT CHARACTERISTICS | ||||||
| Output Low Voltage | VOUT(LOW) | Fault Detection Mode disabled; IOUT = 10 mA | 0.165 | 0.35 | V | |
| Output Low Voltage | VOUT(LOW) | Fault Detection Mode enabled; 5 V, 1 k or 5 V, 3 k option | 0.5 | 1.25 | V | |
| Output Low Voltage | VOUT(LOW) | Fault Detection Mode enabled; 12 V, 1 k option | 1.2 | 3.6 | V | |
| Output High Voltage | VOUT(HIGH) | Fault Detection Mode disabled | VPULLUP | V | ||
| Output High Voltage | VOUT(HIGH) | Fault Detection Mode enabled; 5 V, 1 k or 5 V, 3 k option | 3.75 | 4.5 | V | |
| Output High Voltage | VOUT(HIGH) | Fault Detection Mode enabled; 12 V, 1 k option | 8.4 | 10.8 | V | |
| Fault Voltage | VFAULT | Fault Detection Mode enabled; 5 V, 1 k or 5 V, 3 k option; High fault | 4.5 | V | ||
| Fault Voltage | VFAULT | Fault Detection Mode enabled; 5 V, 1 k or 5 V, 3 k option; Mid fault | 1.25 | 3.75 | V | |
| Fault Voltage | VFAULT | Fault Detection Mode enabled; 5 V, 1 k or 5 V, 3 k option; Low fault | 0.5 | V | ||
| Fault Voltage | VFAULT | Fault Detection Mode enabled; 12 V, 1 k option; High fault | 10.8 | V | ||
| Fault Voltage | VFAULT | Fault Detection Mode enabled; 12 V, 1 k option; Mid fault | 3.6 | 8.4 | V | |
| Fault Voltage | VFAULT | Fault Detection Mode enabled; 12 V, 1 k option; Low fault | 1.2 | V | ||
| Allowable Pullup Voltage | VPULLUP | Fault Detection Mode disabled | 4 | 24 | V | |
| Allowable Pullup Voltage | VPULLUP | Fault Detection Mode enabled; 5 V, 1 k or 5 V, 3 k option | 4.75 | 5.25 | V | |
| Allowable Pullup Voltage | VPULLUP | Fault Detection Mode enabled; 12 V, 1 k option | 11.4 | 12.6 | V | |
| Allowable Pullup Resistor | RPULLUP | Fault Detection Mode disabled | 1 | k | ||
| Allowable Pullup Resistor | RPULLUP | Fault Detection Mode enabled; 5 V, 1 k option | 0.8 | 1.46 | k | |
| Allowable Pullup Resistor | RPULLUP | Fault Detection Mode enabled; 5 V, 3 k option | 1.46 | 3.4 | k | |
| Allowable Pullup Resistor | RPULLUP | Fault Detection Mode enabled; 12 V, 1 k option | 0.9 | 1.1 | k | |
| Allowable Load Capacitor | CLOAD | Fault Detection Mode enabled | 1 | nF | ||
| Output Leakage Current | IOUT(OFF) | Fault Detection Mode disabled; VOUT = VOUT(HIGH) | 10 | A | ||
| Duty Cycle | D | Speed output protocol; Using Reference Target 60-0; Dynamic Threshold option; sinusoidal input signal; fOP < 1 kHz | 45 | 50 | 55 | % |
| Output Rise Time | tr | 10%90%; VPULLUP = 5 V; RPULLUP = 1 k; CLOAD = 2.2 nF | 5 | s | ||
| Output Fall Time | tf | 90%10%; Fault Detection Mode disabled; Fast fall time option | 0.5 | s | ||
| Output Fall Time | tf | 90%10%; Fault Detection Mode disabled; Slow fall time option | 3.5 | s | ||
| Output Fall Time | tf | 90%10%; Fault Detection Mode enabled | 6 | s | ||
| Forward Pulse Width | tw(FWD) | 38 | 45 | 52 | s | |
| Reverse Pulse Width | tw(REV) | 76 | 90 | 104 | s | |
| Propagation Delay | td | Delay from the magnetic signal crossing a switch point threshold to the start of the output transition | 8 | s | ||
| Jitter | 6; sinusoidal input signal; fOP = 1 kHz; BDIFF(pk-pk) = 100 G | 0.13 | target degrees | |||
| Jitter | 6; sinusoidal input signal; fOP = 1 kHz; BDIFF(pk-pk) = 150 G | 0.086 | target degrees | |||
| Jitter | 6; sinusoidal input signal; fOP = 1 kHz; BDIFF(pk-pk) = 200 G | 0.064 | target degrees | |||
2401220954_ALLEGRO-ATS17501PSGATN-SDFUYK-A_C19762046.pdf
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