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Specifications
Voltage - Supply:
4.5V~5.5V
Mfr. Part #:
A1363LLUTR-2-T
Package:
TSSOP-8
Key Attributes
Model Number:
A1363LLUTR-2-T
Product Description
Product Overview
The Allegro A1363 is a low-noise, high-precision, programmable linear Hall-effect current sensor IC designed for high accuracy and resolution without compromising bandwidth. It features proprietary linearly interpolated temperature compensation technology, programmed at the factory, ensuring virtually flat sensitivity and offset across the operating temperature range. This ratiometric sensor IC provides a voltage output proportional to the applied magnetic field and is ideal for HEV inverter, DC-to-DC converter, and electric power steering (EPS) applications. The device offers customer-configurable sensitivity and quiescent output voltage, adjustable via programming on VCC and output pins. It boasts a 90 kHz nominal bandwidth, integrated EEPROM technology for digital temperature compensation, and advanced dynamic offset cancellation techniques for industry-leading sensing resolution.
Product Attributes
- Brand: Allegro
- Package: 8-pin TSSOP (suffix LU)
- Material: Lead (Pb) free, 100% matte tin leadframe plating
- Certifications: AEC-Q100 automotive qualified
Technical Specifications
| Characteristic | Symbol | Conditions | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 4.5 | 5.0 | 5.5 | V | |
| Supply Current | ICC | No load on VOUT | 10 | 15 | mA | |
| Power-On Time | tPO | TA = 25C, CBYPASS = Open, CL = 1 nF, Sens = 2 mV/G, constant magnetic field of 400 G | 78 | s | ||
| Temperature Compensation Power-On Time | tTC | TA = 150C, CBYPASS = Open, CL= 1 nF, Sens = 2 mV/G, constant magnetic field of 400 G | 30 | s | ||
| Undervoltage Lockout (UVLO) Threshold (High) | VUVLOH | TA = 25C, VCC rising and device function enabled | 3.8 | V | ||
| Undervoltage Lockout (UVLO) Threshold (Low) | VUVLOL | TA = 25C, VCC falling and device function disabled | 3.3 | V | ||
| UVLO Enable Delay Time | tUVLOE | TA = 25C, CBYPASS = Open, CL = 1 nF, Sens = 2 mV/G, VCC Fall Time (5 V to 3 V) = 1.5 s | 64 | s | ||
| UVLO Disable Delay Time | tUVLOD | TA = 25C, CBYPASS = Open, CL = 1 nF, Sens = 2 mV/G, VCC Recover Time (3 V to 5 V) = 1.5 s | 14 | s | ||
| Power-On Reset Voltage (High) | VPORH | TA = 25C, VCC rising | 2.6 | V | ||
| Power-On Reset Voltage (Low) | VPORL | TA = 25C, VCC falling | 2.3 | V | ||
| Power-On Reset Release Time | tPORR | TA = 25C, VCC rising | 64 | s | ||
| Internal Bandwidth | BWi | Small signal 3 dB, CL = 1 nF, TA = 25C | 90 | kHz | ||
| Propagation Delay Time | tPD | TA = 25C, magnetic field step of 400 G, CL = 1 nF, Sens = 2 mV/G | 1.9 | s | ||
| Rise Time | tR | TA = 25C, magnetic field step of 400 G, CL = 1 nF, Sens = 2 mV/G | 4.3 | s | ||
| Response Time | tRESPONSE | TA = 25C, magnetic field step of 400 G, CL = 1 nF, Sens = 2 mV/G | 3.8 | s | ||
| Delay to Clamp | tCLP | TA = 25C, Step magnetic field from 800 to 1200 G, CL = 1 nF, Sens = 2 mV/G | 10 | s | ||
| Output Voltage Clamp (High) | VCLP(HIGH) | TA = 25C, RL(PULLDWN) = 10 k to GND | 4.55 | 4.85 | V | |
| Output Voltage Clamp (Low) | VCLP(LOW) | TA = 25C, RL(PULLUP) = 10 k to VCC | 0.15 | 0.45 | V | |
| Output Saturation Voltage (High) | VSAT(HIGH) | TA = 25C, RL(PULLDWN) = 10 k to GND | 4.7 | V | ||
| Output Saturation Voltage (Low) | VSAT(LOW) | TA = 25C, RL(PULLUP) = 10 k to VCC | 400 | mV | ||
| Broken Wire Voltage (High) | VBRK(HIGH) | TA = 25C, RL(PULLUP) = 10 k to VCC | VCC | V | ||
| Broken Wire Voltage (Low) | VBRK(LOW) | TA = 25C, RL(PULLDWN) = 10 k to GND | 100 | mV | ||
| Noise | VN | TA = 25C, CL = 1 nF, BWf = BWi | 1.1 | mGRMS/(Hz) | ||
| Noise | TA = 25C, CL = 1 nF, Sens = 2 mV/G, BWf = BWi | 6.3 | mVp-p | |||
| Noise | TA = 25C, CL = 1 nF, Sens = 2 mV/G, BWf = BWi | 1 | mVRMS | |||
| Initial Unprogrammed Quiescent Voltage Output | VOUT(Q)init | TA = 25C | 2.4 | 2.5 | 2.6 | V |
| Quiescent Voltage Output Programming Range | VOUT(Q)PR | TA = 25C | 2.3 | 2.7 | V | |
| Quiescent Voltage Output Programming Bits | QVO | 9 | bit | |||
| Average Quiescent Voltage Output Programming Step Size | StepVOUT(Q) | TA = 25C | 1.9 | 2.3 | 2.8 | mV |
| Initial Unprogrammed Sensitivity (SENS_COARSE = 00) | Sensinit | TA = 25C | 1 | mV/G | ||
| Sensitivity Programming Range (SENS_COARSE = 00) | SensPR | TA = 25C | 0.6 | 1.3 | mV/G | |
| Coarse Sensitivity Programming Bits | SENS_ COARSE | 2 | bit | |||
| Fine Sensitivity Programming Bits | SENS_FINE | 9 | bit | |||
| Sensitivity Temperature Coefficient | TCSENS | TA=150C, TA= 40C, calculated relative to 25C | 0 | %/C | ||
| Sensitivity Drift Through Temperature Range | SensTC | TA = 25C to 150C | -3.5 | 3.5 | % | |
| Sensitivity Drift Through Temperature Range | SensTC | TA = 40C to 25C | -3.5 | 3.5 | % | |
| Quiescent Voltage Output Temperature Coefficient | TCQVO | TA = 150C, TA = 40C, calculated relative to 25C | 0 | mV/C | ||
| Quiescent Voltage Output Drift Through Temperature Range | VOUT(Q)TC | TA = 25C to 150C | -15 | 15 | mV | |
| Quiescent Voltage Output Drift Through Temperature Range | VOUT(Q)TC | TA = 40C to 25C | -30 | 30 | mV | |
| Lock Bit Programming | EELOCK | 1 | bit | |||
| Linearity Sensitivity Error | LinERR | < 0.25 | 1 | % | ||
| Symmetry Sensitivity Error | SymERR | < 0.25 | 1 | % | ||
| Ratiometry Quiescent Voltage Output Error | RatERRVOUT(Q) | Through supply voltage range (relative to VCC = 5 V) | -1 | 0 | 1 | % |
| Ratiometry Sensitivity Error | RatERRSens | Through supply voltage range (relative to VCC = 5 V) | -2 | < 0.5 | 2 | % |
| Ratiometry Clamp Error | RatERRCLP | Through supply voltage range (relative to VCC = 5 V), TA = 25C | < 1.0 | % | ||
| Sensitivity Drift Due to Package Hysteresis | SensPKG | TA = 25C, after temperature cycling, 25C to 150C and back to 25C | 1.5 1.5 | % | ||
| Sensitivity Drift Over Lifetime | SensLIFE | TA = 25C, shift after AEC-Q100 grade 0 qualification testing | 1 | % | ||
| Package Thermal Resistance | RJA | LU package, estimated, on 4-layer PCB based on JEDEC standard | 145 | C/W | ||
| Operating Ambient Temperature Range | TA | -40 | 150 | C | ||
| Storage Temperature | Tstg | -65 | 165 | C | ||
| Maximum Junction Temperature | TJ(max) | 165 | C | |||
| Package Dimensions (L x W x H) | 8-Pin TSSOP | 6.40 (BSC) x 4.40 (0.10) x 1.10 (MAX) | mm | |||
| Lead Pitch | 0.65 (BSC) | mm | ||||
| Case Thickness | 1 | mm |
2304140030_ALLEGRO-A1363LLUTR-2-T_C2654978.pdf
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